1. Field of the Invention
The present invention relates to a synchronizing signal generator operable responsive to an external synchronizing signal. More specifically, the present invention relates to an improvement in a synchronizing signal generator suited for driving a television camera or cameras with an external synchronizing signal.
2. Description of the Prior Art
In superposing an output signal from a television camera in part in a television broadcast signal as received, combining the output signals from two or more television cameras, and the like to synthesize the television images on a television screen, it is necessary to synchronize a television camera with an external reference synchronizing signal. The present invention is directed to a synchronizing signal generator operable responsive to an external reference synchronizing signal and in particular is aimed to avoid phase disturbance of a horizontal synchronizing signal generated in such a synchronizing signal generator with respect to an external synchronizing signal.
FIG. 1 shows a block diagram of a conventional synchronizing signal generator operable responsive to an external synchronizing signal. Referring to FIG. 1, the synchronizing signal generator shown comprises a voltage controlled oscillator 1 adapted to make oscillation at the central frequency as high as four times the frequency of the subcarrier (14.31818 MHz). The output of the voltage controlled oscillator 1 is applied through an inverter 30 and further through an inverter 31 to a 1/4 frequency divider 2 for frequency dividing the output of the voltage controlled oscillator 1 at the frequency division rate of 1/4 for providing a subcarrier frequency signal and is also applied through the inverter 30 and further through the inverter 31 to a 1/7 frequency divider for frequency dividing the output of the voltage controlled oscillator 1 at the frequency division rate of 1/7. The frequency divided output Ci of the 1/4 frequency divider 2 is applied to a phase comparator 3. The phase comparator 3 is also connected to receive an external subcarrier signal Ce of the frequency 3.579545 MHz. The phase comparator 3 serves to compare the phases of the subcarrier signal Ci from the 1/4 frequency divider 2 and the external subcarrier signal Ce for providing a control voltage signal to the control input of the voltage controlled oscillator 1. Thus, the voltage controlled oscillator 1, the 1/4 frequency divider 2 and the phase comparator 3 constitute a so called phase locked loop. The output of the 1/7 frequency divider 4 is applied to a 1/65 frequency divider 5 for frequency dividing the output of the 1/7 frequency divider 4 at the frequency division rate of 1/65 for providing the output of the frequency as high as two times the frequency of the horizontal synchronizing signal. The output of the 1/65 frequency divider 5 is applied to a first 1/2 frequency divider 7 for frequency dividing the output of the 1/65 frequency divider 5 at the frequency division rate of 1/2. The output of the 1/65 frequency divider 5 is also applied to a 1/525 frequency divider 6 for frequency dividing the output of the 1/65 frequency divider 5 at the frequency division rate of 1/525 for providing the output of the frequency as high as two times the field frequency. The output of the 1/525 frequency divider 6 is also applied to a second 1/2 frequency divider 8 for frequency dividing the output of the 1/525 frequency divider 6 at the frequency division rate of 1/2, thereby to provide the output signal of the same frequency as that of the vertical frame synchronizing signal.
The output of the 1/65 frequency divider 5 and the output of the first 1/2 frequency divider 7 are applied to a line decoder 9, where a horizontal synchronizing signal Hi of the phase which is different from field to field is generated responsive to the output of the first 1/2 frequency divider 7 and the output of the 1/65 frequency divider 5. The output of the 1/525 frequency divider 6 and the output of the second 1/2 frequency divider 8 are also applied to a frame decoder 10, wherein an odd number and even number field determining signals OF (odd field) and EF (even field) are generated. The output from the line decoder 9 and the output from the frame decoder 10 are applied to a composite decoder 11, wherein the output of the line decoder 9 and the output of the frame decoder 10 are synthesized to provide a composite synchronizing signal Cs, a color burst flag signal BF and a composite blanking signal CB. The above described blocks 2, 4, 5, 6, 7, 8, 9, 10 and 11 may be implemented in an integrated circuit L and such an integrated circuit for a synchronizing signal generator is commercially available from Fairchild Camera Instruments, Inc. as identified as MOS 3262 A.
An external vertical synchronizing signal Ve is applied through a delay circuit 12 for delaying the input signal by less than 1/60 second to the 1/525 frequency divider 6 by way of a reset signal. Similarly an external horizontal synchronizing signal He is applied through a delay circuit 13 for delaying the signal to the 1/7 frequency divider 4, the 1/65 frequency divider 5 and the first 1/2 frequency divider 7 as a reset signal. Since the integrated circuit L is structured such that the internal horizontal synchronizing signal Hi is obtained from the line decoder 9 with a given delay time from the reset timing responsive to the external horizontal synchronizing signal He and the internal vertical synchronizing signal Vi is obtained from the frame decoder 10 with another delay time from the reset timing responsive to the external vertical synchronizing signal Ve, respectively, the delay circuits 13 and 12 are provided to delay the above described external horizontal and vertical synchronizing signals He and Ve, respectively, by given time periods so that the phases of the internal horizontal and vertical synchronizing signals Hi and Vi come to coincide with each other. The delay circuits 13 and 12 are also aimed to set the pulse width of the horizontal and vertical reset signals.
In such a conventional synchronizing signal generator, however, it has been noted that a problem is encountered. More specifically, in such a synchronizing signal generator, the external subcarrier signal Ce to be applied to the phase comparator 3 is not always in the same predetermined phase relation with the external horizontal synchronizing signal He. The reason is that even if these external subcarrier signal Ce and external horizontal synchronizing signal He are generated by the use of a common external synchronizing signal source, the amounts of the phase delay which the external subcarrier signal Ce and the external horizontal synchronizing signal He undergo are different depending on the lenghts of the cable connecting the synchronizing signal generator to such external synchronizing signal source. Thus, even when the oscillation output of the voltage controlled oscillator 1 to be phase locked to the external subcarrier signal Ce is in a given phase relation with the external horizontal synchronizing signal He, the phase relation of the internal horizontal synchronizing signal Hi is not properly determined.
FIG. 2 shows wave forms of various signals in the FIG. 1 diagram for explaining the operation of the FIG. 1 diagram. Referring to FIG. 2, assuming that a phase relation is established such that the fall of the output (a) from the voltage controlled oscillator 1 and the rise of the output (b) from the delay circuit 13 for determining the reset timing coincide with each other, then even a slight shift leftward or rightward of the timing of the rise of the above described wave form (b) by virtue of a temperature drift or the like at the respective reset timing for each one horizontal line makes a difference in start of a counting operation in the frequency divider 4 depending on the situation, such as from the pulse n, the next pulse n+1 or the like. As a result, an internal horizontal synchronizing pulse (c) or (d) as different of the phase by one cycle of the reference oscillation pulse (a), i.e. 0.07 microsecond is obtained from the synchronizing signal generator and in addition which internal horizontal synchronizing pulse (c) or (d) should appear at every reset timing for each horizontal line is not inherently determined. As a matter of practice, however, the internal horizontal synchronizing signal of the wave form (c) or (d) appears at random or possibly appears alternately for each horizontal line, as comfirmed through experimentation and if television cameras are driven with such a horizontal synchronizing signal, an image on the television screen is distorted in the vertical direction. Referring to FIG. 2, it is pointed out that the leading edge of the internal horizontal synchronizing pulse (c) has been shown as delayed with respect to the trailing edge of the delay circuit output (b), because of an inherent delay in the integrated circuit L.